Welcome

June 12-15, 2018:  Conference, Beijing, China (YouTube)

Sponsored by ACM/SIGARCH

ACM International Conference on Supercomputing (ICS) is the premier international forum for the presentation of research results in high-performance computing systems. The 32nd conference (ICS-2018) will be held on June 12-15 in Beijing, China.

The registration website is open, you can Register Now!

Call for Participant

ICS-2018 provides a high-quality forum for scientists, engineers to present their latest studies in this rapidly changing field. In this year, we will have Workshops and Tutorial on Tuesday, June 12 as well as the Keynote Speeches and Technical Main Program from Wednesday, June 13 to Friday, June 15. The reception and social event are tentatively on June 12 and 14, respectively.

We are looking forward to seeing your participant for ICS-2018. For more details on the conference, invitation letter, traveling, co-located event as well as other helps, please feel free to drop emails to the General Chairs (Lei Liu and Michael, email: liulei2010-AT-ict.ac.cn).

ICS 2018 General Chairs’ Welcome


Registration & Travel Information

Registration Information (Link)
Hotel Reservation (Link)
Invitation letter: attending the conference, please contact the general chairs (liulei2010-AT-ict.ac.cn) to get an invitation letter. Moreover, If you need an invitation letter for applying for a Chinese visa, please provide the information according to this doc to general chairs.


Main Program (June 13-15, 2018)

Session Information (Link)
We have ACM-W session with the main conference. Looking forward your participant and registration.


Workshop & Tutorials (June 12, 2018)

Workshop Information

    -Full Day:

  • International Workshop on High Performance Computing for Advanced Modeling and Simulation in Nuclear Energy and Environmental Science (HPCMS 2018)
  • Workshop on Big scientific data benchmarks, Architecture, and Systems (SDBA'18)
  • Reconfigurable Acceleration in Datacenters (ReconfigAccel 2018)

    -Half Day:

  • International Workshop on HPC Supported Data Analytics for Edge Computing (HiDEC 2018)
  • The Next Generation Cloud: Unikernel Is Coming! (TNGCUIK 2018)
  • International Workshop on Large-Scale Deep Learning on Modern Heterogeneous Supercomputers (DLMHS-18)
  • International Workshop on Memory Architectures and Systems with Emerging Technologies (IWMASET 2018)

Tutorial Information

    -Half Day:

  • Vector Architecture Exploration with gem5 (Link)

All the accepted workshop papers will be published by Springer (author optional).


Conference Topics:

The conference will include results from the following topics:

  • Programming and execution models for high-performance computing;
  • Static and dynamic compilation optimization techniques to exploit all aspects of high performance architectures;
  • Computer Architectures and accelerators aiming to support high-performance computing;
  • Runtime and system software support for high-performance and heterogeneous computing;
  • New computational models and algorithms for high performance computing systems;
  • Security aspect of datacenters; how can we protect datacenters and how can we use them to expose security weaknesses;
  • New applications and workload analysis;
  • The use of machine learning to design/analyze large-scale computing system.

The submission is over. The review process will include a rebuttal period. The important dates are given below:

Abstract submission: January 19, 2018 AOE
Paper submission: January 26, 2018 AOE
Jan 29, 2018. 11:59:59 pm EST (Hard Deadline)
Rebuttal period: March 12-19, 2018 AOE
Author notification: March 25, 2018 AOE
Camera Ready: May 1, 2018

Call for Papers

June 12-15, 2018:  Conference, Beijing, China

Sponsored by ACM/SIGARCH

ACM International Conference on Supercomputing (ICS) is the premier international forum for the presentation of research results in high-performance and supercomputing. The 32nd conference (ICS 2018) will be held on June 12-15 in Beijing, China. CFP in Sigarch and Wiki.

Papers are solicited on all aspects of research, development, and application of high-performance and super-computing systems, including but not limited to the following:

  • Programming and execution models for high-performance computing;
  • Static and dynamic compilation optimization techniques to exploit all aspects of high performance architectures;
  • Computer Architectures and accelerators aiming to support high-performance computing;
  • Runtime and system software support for high-performance and heterogeneous computing;
  • New computational models and algorithms for high performance computing systems;
  • Security aspect of datacenters; how can we protect datacenters and how can we use them to expose security weaknesses;
  • New applications and workload analysis;
  • The use of machine learning to design/analyze large-scale computing system.

The review process will include a rebuttal period, and the papers will be judged based on novelty, technical soundness, and potential impact on the field.

Important Dates

Abstract submission: January 19, 2018 AOE
Paper submission: January 26, 2018 AOE
Jan 29, 2018. 11:59:59 pm EST (Hard Deadline)
Rebuttal period: March 12-19, 2018 AOE
Author notification: March 25, 2018 AOE
Camera Ready: May 1, 2018

AOE (Anywhere on Earth) dates shown above mean the deadlines are at 11:59pm UTC -12:00 of the days. The above dates are tentative and subject to change. Consult the conference website for the most up-to-date scheduling information.

Submissions

The submission site is over. Submissions should be a maximum of ten (10) pages, including references.

Submissions (both abstract and paper) should be prepared for double blind review, i.e., without author names, or other identifying material in the submission. Authors should refer to themselves in the 3rd person when citing their own work.

The submission system requests information about the authors. This information will not be given to the reviewers.

Call for Workshop Proposals

The organizers of the 32nd ACM International Conference on Supercomputing (ICS'18) call for proposals for workshops to be held in conjunction with ICS'18. Workshops should provide forums for discussion among researchers and practitioners on focused topics or emerging research areas relevant to the community of high-performance computing. Workshop organizers may structure workshops as they see fit, including invited talks, panel discussions, presentations of work in progress, fully peer-reviewed papers, or some combination of the above. Workshops could be scheduled for half a day or a full day on June 12th, 2018, depending on interests, space constraints, and the organizer’s preference. Organizers should design workshops for approximately 20-40 participants, to balance the impact and effective discussion.

The deadline for submission of a proposal is November 1st, 2017 January 15th, 2018. We strongly encourage workshop organizers to submit their proposals early so that there is enough time to organize the workshop program before the conference. We also encourage proposals for new workshops that have not been held before.

Workshop proposals should include the followings:

  • The name and the acronym of the workshop
  • A description (0.5-1 page) of the theme of the workshop
  • A description (one paragraph) on the relevance of the theme of the workshop to ICS
  • A list of topics of interest
  • The names and affiliations of the workshop organizers, and if applicable, of a significant portion of the program committee
  • A description of the expected structure of the workshop (papers, invited talks, panel discussions, etc.)
  • Data about previous offerings of the workshop (if applicable), including the attendance, the numbers of papers or presentations submitted and accepted, and the links to the corresponding websites
  • A publicity plan for attracting submissions and attendees. Please also include expected number of submissions, accepted papers, and attendees that you anticipate for a successful workshop.

Workshop co-chairs

  • Pen-Chung Yew, University of Minnesota at Twin Cities. Email address: yew@umn.edu
  • Shigang Li, Institute of Computing Technology, Chinese Academy of Sciences. Email address: shigangli.cs@gmail.com

Proposal Submission

  • Please send your proposal in PDF format via email to the ICS'18 Workshops Chairs (yew@umn.edu and shigangli.cs@gmail.com)

Important Dates

Workshop Proposals Due: November 1st, 2017
January 15th, 2018
Notification of Acceptance: November 15th, 2017
February 10th, 2018

Keynotes

We are honored to have the following keynote speakers at ICS 2018.


Mateo Valero

Bio: Mateo Valero obtained his Telecommunication Engineering Degree from the Technical University of Madrid (UPM) in 1974 and his Ph.D. in Telecommunications from the Technical University of Catalonia (UPC) in 1980. Since 1974 he is a professor in the Computer Architecture Department at UPC, in Barcelona and since 1983 he is full professor. His research interests focuses on high performance architectures. He has published approximately 500 papers, has served in the organization of more than 300 International Conferences and he has given more than 300 invited talks. He is the director of the Barcelona Supercomputing Centre, the National Centre of Supercomputing in Spain.

Hironori Kasahara

Bio: Hironori Kasahara is a professor in the Department of Computer Science and Engineering at Waseda University. He is an IEEE Fellow, an IPSJ Fellow, a Golden Core Member of the IEEE Computer Society, a professional member of the IEEE Eta Kappa Nu, a member of the Engineering Academy of Japan and the Science Council of Japan. He received a PhD in 1985 from Waseda University, Tokyo, joined its faculty in 1986, and has been a professor of computer science since 1997 and a director of the Advanced Multicore Research Institute since 2004. He was a visiting scholar at University of California, Berkeley, and the University of Illinois at Urbana–Champaign’s Center for Supercomputing R&D.

Invited Talk


Guang R. Gao

Bio: Guang R. Gao received his B.S. degree in Electrical Engineering from Tsinghua University in 1968, his M.S. and Ph. D. degrees in computer science from MIT in 1982 and 1986, respectively. Currently, he is a Named Professor Emeritus at the ECE Department of University of Delaware, Newark, the founding director of Computer Architecture and Parallel System Laboratory (CAPSL). Dr. Gao has been a endowed visiting professor at Tsinghua University and a Visiting Professor for several top Chinese Universities.Dr. Gao’s research interests include high-performance computing and dataflow models, computer architecture and systems, compiler technology and runtime systems, program analysis, mapping and optimization under dataflow moels. Dr. Gao has been a Principal Investigator or Co-Investigator of a number of high-impact research projects in Parallel Computing sponsored by the National Science Foundation, DARPA, DOE, DOD and other US and Canadian government agencies.He was elected to an IEEE Fellow in 2007 and ACM Fellow in 2007. He is the recipient of the 2017 IEEE Computer Society (CS) B. Ramakrishna Rau Technical Award “For contributions to compiler techniques and microarchitectures for instruction-level and thread-level parallel computing.”

Jian Ouyang

Bio: Jian ouyang, Baidu principle architect, is responsible for Baidu silicon and architecture team. He is looking at novel AI architecture and system for cloud, autonomous driving and intelligent edge device. In the past several years, he also worked on storage and big data system. he have published paper on ASPLOS 2014(and best paper nominated), Hotchips 2014 /2016/2017, etc.

Wan Wei

Bio: Wan Wei, vice general manager of Sugon HPC product division, obtained his B.S. degree of E&E from Tsinghua University in 2005, is now responsible for Sugon's high performance fabric team. In the past several years, he also worked on linux kernel, computer network, security and machine learning.

Registration

Early Bird Registration ends  May 12th, 2018. To receive discounted rates, registrations must be submitted and paid in full by 11:59 pm UTC+8 (Chinese Standard Time) on  May 12th, 2018.

Registration A
Foreign attendees please click here to finish registration. Register Now!

Registration B
Chinese attendees who request invoice please go through Register B to finish registration. (需要发票的中国参与人员请点击 Register B 完成注册). Register Now!

Note: 1. Please make sure that your ACM account is active now, if you would like to register with role of ACM member.
          2. If you would like to join ACM, please Click here!

Payment Instructions for Chinese Attendees

1.1 银行汇款方式缴纳:
请务必在汇款单上注明"ICS2018+参会人姓名"。
开户名:中国科学院计算技术研究所
账号:0200004509088123135
开户行:工行海淀西区支行
地址:北京市海淀区科学院南路6号
如有问题,请联系:17611481669
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转账时请务必备注"ICS2018+参会人姓名"。
支付宝账号:xiemy1992@163.com(谢梦瑶)

2.现场注册费用缴纳:
2018年06月11日---12日两个全天,于会议注册现场进行付费,注册当晚交付发票。

现场付款方式仅以下三种:

  • 现金支付
  • 支付宝转账
  • 微信支付

    3.信息确认 (重要):
    会议注册费转账完成后,请在2天内将转账信息(附汇款凭证或支付宝转账截图)和“注册信息表”发送至ics_registration@ict.ac.cn的邮箱。
    注册以及转账成功与否以本邮箱发送的确认邮件为准。
    若有疑问,请随时发送邮件至本邮箱取得联系。
    点此下载注册信息表 Registration.docx

  • Conference Venue

    The 2018 conference will be held in Beijing International Convention Center:
    No.8 Beichen Dong Road, Chaoyang District, Beijing.
    Foreign attendees please click here to get more information about the venue: Beijing International Convention Center English Link
    Chinese attendees please click here to get more information about the venue. (中宾请点此访问场地方主页): Beijing International Convention Center Chinese Link

    Location in the map:


    Meeting room:


    Reception lawn:

    Accommodation:

    Hotel Information

    Beijing Continental Grand Hotel

    The official conference hotel is the Beijing Continental Grand Hotel.
    Foreign attendees please click here to finish hotel reservation: ICS-2018 Hotel Reservation English Link
    Chinese attendees please click here to finish hotel reservation. (中宾请点此预订酒店): ICS-2018 Hotel Reservation Chinese Link

    Other hotels nearby:

    V-Continent Beijing Parkview Wuzhou Hotel (five stars, 4min walk)
    Beijing Huiyuan Service Apartment (4 stars, 8min walk)
    National Jade Hotel (4 stars, 11min walk)
    Aoyou Hotel (3 stars, 12min walk)
    Yayuncun Hotel Beijing (3 stars, 11min walk)

    Excursion

    The 2018 conference will be held in Beijing. Beijing is the capital of China, the political and cultural center of the country and the hub of international exchanges. It is also an ancient capital of more than 3,000 years. There are many historical sites and cultural landscapes. We will visit the Palace Museum during the conference (YouTube).

    The Palace Museum

    The Palace Museum, also known as the Forbidden City, is The Ming and Qing Dynasties Palace. It is the largest and most complete existing ancient buildings in China (YouTube).


    Treasures

    The Palace Museum contains a large number of treasures.


    Laoshe Tea House

    In the evening, we can enjoy Beijing traditional tea culture, opera culture and other Chinese traditions and cultures in Laoshe Tea House.

    We will have dinner in Laoshe Tea House.

    Tea Tasting and Shadow Play

    Beijing Opera and Kung Fu Tea

    Conference Program

    13/June (Wednesday)

    8:50-9:00 Opening (General Chairs: Michael Gschwind, Lei Liu)
    9:00-10:00 Keynote 1: Prof. Hironori Kasahara - U. Waseda, Japan
    10:00-10:15 Break
    10:15-12:15 Session 1: File system, I/O and Storage System
    12:15-1:15 Lunch
    1:15-1:45 Invited talk 1: Jian Ouyang - Baidu
    1:45-3:15 Session 2A: GPUs-I: Execution Model              Session 2B: GPUs-II: Algorithm
    3:15-3:30 Break
    3:30-5:00 Session 3A: Architecture Session 3B: Accelerator
    5:00-6:00 ACM-W Event - Catherine Lang
    6:00-9:00 Reception

    14/June (Thursday)

    8:15-9:15 Keynote 2: Prof. Mateo Valero - BSC Barcelona
    9:15-10:45 Session 4A: Application Framework Session 4B: Runtime System and Library
    10:45-11:00 Break
    11:00-12:30 Session 5A: Program Analysis Session 5B: System Design
    12:30-1:00 Lunch
    1:00-9:00 Excursion + Social Event

    15/June (Friday)

    9:00-9:30 Invited talk 2: Wan Wei - Sugon
    9:30-10:30 Session 6: Parallel Algorithm
    10:30-10:45 Break
    10:45-12:15 Session 7: Compiler and OS
    12:15-1:30 Lunch
    1:30-2:00 Invited talk 3: Prof. Guang R. Gao - University of Delaware
    2:00-2:30 Round Table discussion
    2:30-4:00 Session 8: Optimization and Performance Tuning
    4:00-4:15 Adjourn

    Detailed Program

    Keynote 1: Automatic Multigrain Parallelization, Memory Optimization and Power Reduction Compiler for Multicore Systems (13/June, 9:00 am-10:00 am) - Prof. Hironori Kasahara

    Abstract:

    Session 1: File system, I/O and Storage System (13/June, 10:15 am-12:15 pm)

    PFault: A General Framework for Analyzing the Reliability of High-Performance Parallel File Systems - Jinrui Cao, Om Rameshwar Gatla, Mai Zheng (New Mexico State University), Dong Dai, Vidya Eswarappa, Yan Mu, Yong Chen (Texas Tech University)
    Rethinking Node Allocation Strategy for Data-intensive Applications in Consideration of Spatially Bursty I/O - Jie Yu, Guangming Liu, Xin Liu, Wenrui Dong, Xiaoyong Li, Yusheng Liu (College of Computer, National University of Defense Technology)
    PA-SSD: A Page-Type Aware TLC SSD for Improved Write/Read Performance and Storage Efficiency - Wenhui Zhang, Qiang Cao, Hong Jiang, Jie Yao (Department of Computer Science and Technology, Huazhong University of Science and Technology)
    IRIS: I/O Redirection via Integrated Storage - Anthony Kougkas, Hariharan Devarajan, Xian-He Sun (Illinois Institute of Technology)

    Invited talk 1: XPU – A Programmable AI Processor Architecture for Baidu Diverse Workloads
                          (13/June, 1:15 pm-1:45 pm) - Jian Ouyang

    Abstract: Baidu has a wide-range AI scenarios, including cloud, autonomous driving and intelligent home devices. The diverse scenarios and workload motivate us to explore general-purpose architecture for AI computing. In this case, we propose XPU. It is an instruction granularity programmable AI processor. In this talk, I will shared the work on XPU in Baidu.

    Session 2A: GPUs-I: Execution Model (13/June, 1:45 pm-3:15 pm)

    GRU: Exploring Computation and Data Redundancy via Partial GPU Computing Result Reuse - Husheng Zhou, Soroush Bateni, Cong Liu (University of Texas at Dallas)
    Warp-Consolidation: A Novel Execution Model for Modern GPUs - Ang Li (Pacific Northwest National Lab), Weifeng Liu (Norwegian University of Science and Technology), Linnan Wang (Brown University), Kevin Barker (Pacific Northwest National Lab), Shuaiwen Leon Song (Pacific Northwest National Lab and William & Mary)
    Classification-Driven Search for Effective SM Partitioning in GPU Multitasking - Xia Zhao (Ghent University), Zhiying Wang (National University of Defense Technology), Lieven Eeckhout (Ghent University)

    Session 2B: GPUs-II: Algorithm (13/June, 1:45 pm-3:15 pm)

    The Broker Queue: A Fast, Linearizable FIFO Queue for Fine-Granular Work Distribution on the GPU - Bernhard Kerbl, Joerg H. Mueller, Michael Kenzel, Dieter Schmalstieg, Markus Steinberger (Graz University of Technology)
    Analysis-driven Engineering of Comparison-based Sorting Algorithms on GPUs - Ben Karsin (University of Hawaii at Manoa), Volker Weichert (Goethe University Frankfurt), Henri Casanova (University of Hawaii at Manoa), John Iacono (New York University), Nodari Sitchinava (University of Hawaii at Manoa)
    Optimizing Tensor Contractions in CCSD(T) for Efficient Execution on GPUs - Jinsung Kim, Aravind Sukumaran Rajam, Changwan Hong (The Ohio State University), Ajay Panyala (Pacific Northwest National Laboratory) , Rohit Kumar Srivastava (The Ohio State University), Sriram Krishnamoorthy (Pacific Northwest National Laboratory), P. Sadayappan (The Ohio State University)

    Session 3A: Architecture (13/June, 3:30 pm-5:00 pm)

    A two-phase recovery mechanism - Zhaoxiang Jin, Soner Onder (Michigan Technological University)
    HALO: A Hierarchical Memory Access Locality Modeling Technique For Memory System Explorations - Reena Panda, Lizy John (University of Texas at Austin)
    High-Performance, Low-Complexity Deadlock Avoidance for Arbitrary Topologies/Routings - Jose A. Pascual, Javier Navaridas (The University of Manchester)

    Session 3B: Accelerator (13/June, 3:30 pm-5:00 pm)

    ComPEND: Computation Pruning through Early Negative Detection for ReLU in a Deep Neural Network Accelerator - Dongwoo Lee, Sungbum Kang, Kiyoung Choi (Neural Processing Research Center (NPRC), Seoul National University)
    CELIA: A Device and Architecture Co-Design Framework for STT-MRAM-Based Deep Learning Acceleration - Hao Yan, Hebin R. Cherian, Ethan C. Ahn, Lide Duan (University of Texas at San Antonio)
    Directive-Based, High-Level Programming and Optimizations for High-Performance Computing with FPGAs - Jacob Lambert (University of Oregon), Seyong Lee (Oak Ridge National Lab), Jungwon Kim (Oak Ridge National Lab), Jeffrey S. Vetter (Oak Ridge National Lab), Allen D. Malony (University of Oregon)

    ACM-W Event - Catherine Lang (13/June, 5:00 pm-6:00 pm)

    Keynote 2: From Classical to Runtime Aware Architectures and Beyond
                      (14/June, 8:15 am-9:15 am) - Prof. Mateo Valero

    Abstract: When uni-cores were the norm, Instruction Level Parallelism (ILP) and Data Level Parallelism (DLP) were exploited to increase the number of instructions executed per cycle. The main hardware approaches exploiting ILP were Very Long Instruction Word (VLIW) processors, which require to statically determine dependencies between instructions, and Superscalar designs, which dynamically detect and execute multiple independent instructions in parallel by using several execution units. Computer architects started to combine superscalar processors with pipelined, out-of-order and speculative execution to mitigate the increasingly large memory latencies. In this context, simple Instruction Set Architectures (ISA) allowed to decouple the hardware design from the software.
      More recently, the traditional ways to increase hardware performance to the rate predicted by the Moore's Law vanished. The integration of symmetric multiprocessors on a single chip has compensated the frequency stagnation problem. However, such kind of multi-core architectures do not decouple the hardware design from the software stack in the same easy way as uniprocessors did. They face multiple problems in terms of power consumption, programmability or memory latency. The solution is to give more responsibility to the parallel runtime system and to let it tightly collaborate with the hardware. The runtime has to drive the design of multi-core architectures.
      In this talk, we introduce an approach towards a Runtime-Aware Architecture (RAA), a massively parallel architecture designed from the runtime's perspective. RAA aims at supporting the activity of the parallel runtime system in three ways: First, to enable fine-grain tasking; second, to improve the performance of the memory subsystem by exposing hybrid hierarchies to the runtime; and, third, by using vector units. During the talk, we will give an overview of the problems RAA aims to solve and provide some examples of hardware components supporting the activity of the parallel runtime system.
      This talk also describes several ways to improve the RAA concept even more. They consist in exploiting the dynamic information available at the hardware level by using artificial intelligence approaches.

    Session 4A: Application Framework (14/June, 9:15 am-10:45 am)

    ReGraph: A Graph Processing Framework that Alternately Shrinks and Repartitions the Graph - Xue Li, Mingxing Zhang, Kang Chen, Yongwei Wu (Tsinghua University)
    cuMBIR: An Efficient Framework for Low-dose X-ray CT Image Reconstruction on GPUs - Xiuhong Li, Yun Liang, Wentai Zhang, Taide Liu, Haochen Li, Guojie Luo, Ming Jiang (Peking University)
    Zwift: A Programming Framework for High Performance Text Analytics on Compressed Data - Feng Zhang (Renmin University of China), Jidong Zhai (Tsinghua University), Xipeng Shen (North Carolina State University), Onur Mutlu (ETH Zürich), Wenguang Chen (Tsinghua University)

    Session 4B: Runtime System and Library (14/June, 9:15 am-10:45 am)

    Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies - Isaac Sánchez Barrera, Miquel Moretó, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas (Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya)
    Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs - Lluc Alvarez, Marc Casas, Miquel Moreto, Jesus Labarta, Eduard Ayguade, and Mateo Valero (Barcelona Supercomputing Center)
    Optimizing Data Aggregation by Leveraging the Deep Memory Hierarchy on Large-scale Systems - Francois Tessier, Paul Gressier, Venkatram Vishwanath (Argonne National Laboratory)

    Session 5A: Program Analysis (14/June, 11:00 am-12:30 pm)

    Automated Analysis of Time Series Data to Understand Parallel Program Behaviors - Lai Wei, John Mellor-Crummey (Rice University)
    ChplBlamer: A Data-centric and Code-centric Combined Profiler for Multi-locale Chapel Programs - Hui Zhang, Jeffrey K. Hollingsworth (Department of Computer Science, University of Maryland-College Park)
    ProfDP: A Lightweight Profiler to Guide Data Placement in Heterogeneous Memory Systems - Shasha Wen (College of William and Mary), Lucy Cherkasova (ARM Research), Felix Xiaozhu Lin (Purdue ECE), Xu Liu (College of William and Mary)

    Session 5B: System Design (14/June, 11:00 am-12:30 pm)

    Phase-Aware Web Browser Power Management on HMP Platforms - Nadja Peters, Sangyoung Park, Daniel Clifford, Sami Kyostila, Ross McIlroy, Benedikt Meurer, Hannes Payer (Google Inc.), Samarjit Chakraborty (Technical University of Munich)
    Demystifying Cache Policies for Photo Stores at Scale: A Tencent Case Study - Ke Zhou, Si Sun, Hua Wang (HuaZhong University of Science and Technology), Ping Huang, Xubin He (Temple University), Rui Lan, Wenyan Li (Tencent Inc.), Wenjie Liu (Temple University), Tianming Yang (Huanghuai University)
    Isometry: A Path-Based Distributed Data Transfer System - Zhihao Jia (Stanford University), Sean Treichler (NVIDIA), Galen Shipman and Pat McCormick (LANL), Alex Aiken (Stanford University)

    Invited talk 2: Network Architecture Practices for Large Scale Expandable HPC
                          (15/June, 9:00 am-9:30 am) - Wan Wei

    Abstract: Brief introduction of Sugon's consideration and practical experience to use torus network topology in large scale HPC.

    Session 6: Parallel Algorithm (15/June, 9:30 am-10:30 am)

    Accurate, Fast and Scalable Kernel Ridge Regression on Parallel and Distributed Systems - Yang You, James Demmel (UC Berkeley), Cho-Jui Hsieh (UC Davis), Richard Vuduc (Georgia Institute of Technology)
    Dynamic Load Balancing for Compressible Multiphase Turbulence - Keke Zhai, Tania Banerjee, David Zwick, Jason Hackl, and Sanjay Ranka (University of Florida)

    Session 7: Compiler and OS (15/June, 10:45 am-12:15 pm)

    Revisiting Loop Tiling for Datacenters: Live and Let Live - Jiacheng Zhao, Huimin Cui, and Yalin Zhang (State Key Laboratory of Computer Architecture, Institute of Computing Technology, CAS), Jingling Xue (School of Computer Science and Engineering, University of New South Wales), Xiaobing Feng (State Key Laboratory of Computer Architecture, Institute of Computing Technology, CAS)
    Sculptor: Flexible Approximation with Selective Dynamic Loop Perforation - Shikai Li, Sunghyun Park, Scott Mahlke (University of Michigan, Ann Arbor)
    A Case for Granularity Aware Page Migration - Jee Ho Ryoo (ARM Inc.), Lizy K. John (UT-Austin), Arkaprava Basu (Indian Institute of Science)

    Invited talk 3: Future of HPC and Smart Machines: A View of System Challenges and Opportunities
                          (15/June, 1:30 pm-2:00 pm) - Prof. Guang R. Gao

    Abstract:

    Session 8: Optimization and Performance Tuning (15/June, 2:30 pm-4:00 pm)

    Towards Efficient SpMV on Sunway Many-core Architectures - Changxi Liu (School of Computer Science and Engineering, Beihang University), Biwei Xie (State Key Laboratory of Computer Architecture, Institute of Computing Technology, Chinese Academy of Sciences), Xin Liu (National Research Centre of Parallel Computer Engineering and Technology), Wei Xue (Department of Computer Science, Tsinghua University), Hailong Yang (School of Computer Science and Engineering, Beihang University), Xu Liu (Department of Computer Science, College of William and Mary)
    On Optimizing Distributed Tucker Decomposition for Sparse Tensors - Venkatesan Chakaravarthy, Jee W Choi, and Douglas J Joseph (IBM Research), Prakash Murali (Princeton University), Yogish Sabharwal, S Shivmaran, Dheeraj Sreedhar (IBM Research)
    Bootstrapping Parameter Space Exploration for Fast Tuning - Jayaraman Thiagarajan, Nikhil Jain, Rushil Anirudh, Alfredo Gimenez (Lawrence Livermore National Laboratory), Rahul Sridhar (University of California, Irvine), Aniruddha Marathe (Lawrence Livermore National Laboratory), Tao Wang (North Carolina State University), Murali Emani, Abhinav Bhatele, Todd Gamblin (Lawrence Livermore National Laboratory)

    Organizing Committee (Tentative)

    General Chairs:
    Michael Gschwind, IBM
    Lei Liu, ICT, CAS

    Program Chair:
    Avi Mendelson, Technion
    Guangming Tan, ICT, CAS

    Workshop Chairs:
    P-C Yew, University of Minnesota
    Shigang Li, ICT, CAS

    Publicity Chairs:
    Wenguang Chen, Tsinghua University
    Kelly Shaw, University of Richmond
    Yuan Xie, University of California, Santa Barbara
    Yunquan Zhang, ICT, CAS
    Amro Award, University of Central Florida

    Registration Chair:
    Yang Hu, University of Texas, Dallas

    Submission Chair:
    Bin Ren, College of William & Mary

    Web Chair:
    Hongna Geng, ICT, CAS

    Finance Chair:
    Zhigang Huo, ICT, CAS

    Sponsor Chairs:
    Wenguang Wang, VMware, USA
    Zhenman Fang, University of California, Los Angeles & Xilinx
    Yang Chen, MSRA

    Publication Chair:
    Shuaiwen Leon Song, PNNL

    Local Arrangements:
    Mengyao Xie, ICT, CAS
    Xiaobing Feng, ICT, CAS

    Program Committee
    Tarek Abdelrahman, University of Toronto
    Gagan Agrawal, Ohio-State University
    Hong An, USTC
    Taisuke Boku, Tausyke University
    Zoran Budimlic, Rice University
    Anton Burtsev, University of California, Irvine
    Ali R. Butt, Virginia Tech
    Marc Casas, Barcelona Supercomputing Center
    Wenguang Chen, Tsinghua University
    Chen Ding, University of Rochester
    Mattan Erez, University of Texas, Austin
    Yaoqing Gao, Huawei
    Saugata Ghose, CMU
    Maike Gilliot, Teratec, France
    Minyi Guo, Shanghai Jiao Tong University
    Rajiv Gupta, University of California, Riverside
    Howie Huang, George Washington University
    Jose Joao, ARM
    David Kaeli, Northeastern University
    Arun Kejariwal, UC Irvine
    Yun (Eric) Liang, Peking University
    Chu-Cheow Lim, Qualcomm
    Mieszko Lis, University of British Columbia
    David Liu, University of Birmingham
    Weifeng Liu, Norwegian University of Science and Technology
    Sally McKee, Clemson University/Rambus
    Saurav Muralidharan, Nvidia
    Onur Mutlu, ETH, Zurich
    Sreepathi Pai, University of Rochester
    Dhabaleswar Panda, Ohio-State University
    Gennady Pekhimenko, University of Toronto
    Alex Rico, ARM
    Martin Schulz, TU Munich
    Min Si, Argonne National Laboratory
    Lavanya Subramanian, Intel
    Nathan Tallent, PNNL
    Osman Unsal, UPC: Universitat Politècnica de Catalunya
    Hans Vandierendonck, Queen's University Belfast
    Anand Venkat, Intel
    Keval Vora, University of California, Riverside
    Hao Wang, Virginia Tech
    Zhenlin Wang, Michigan Technological University
    Zane Wei, Huawei
    Guoqing Xu, University of California, Irvine
    Qing Yi, University of Colorado
    Zhibin Yu, Shenzhen Institutes of Advanced Technology, CAS
    Eddy Zhang, Rutgers, The State University of New Jersey

    Steering Committee

    Utpal Banerjee, USA
    Laxmi Bhuyan, University of California Riverside, USA
    Fred Chong, University of Chicago, USA
    Kemal Ebcioglu, Global
    Kyle Gallivan, Florida State University, USA
    Michael Gerndt, Technical University of Munich, Germany
    James Goodman, USA
    Michael Gschwind, IBM, USA
    Mahmut Kandemir, Pennsylvania State University, USA
    Sally A. McKee, Chalmers University of Technology, Sweden
    Jose Moreira, IBM, USA
    Onur Mutlu, CMU, USA
    Alex Nicolau, University of California Irvine, USA
    Ozcan Ozturk, Bilkent University, Turkey
    Constantine Polychronopoulos, University of Illinois at Urbana-Champaign, USA
    Lawrence Rauchwerger, Texas A&M University, USA
    Valentina Salapura, IBM, USA
    Vivek Sarkar, Rice University, USA
    John Sopka, EMC, USA
    Per Stenstrom, Chalmers University, Sweden
    Mateo Valero, Technical University of Catalonia, Spain
    Alex Veidenbaum, University of California Irvine, USA
    Harry Wijshoff, Leiden University, The Netherlands

    Financial Support

    ICS 2018 encourages sponsorship from industry, government, and institutions. Sponsorship can take the form of monetary and in-kind contributions. In general, contributions are used for various purposes ranging from honoraria for keynote speakers, prizes for best papers / posters, improved social events (receptions, conference dinner), special consideration on registration costs, and travel support for students. Targeted sponsorship for specific ICS 2018 support is welcomed and a list of opportunities is provided below.

    Sponsorship Levels

    There are four ranges of sponsorship levels for ICS 2018. These are listed below along with their specific benefits. All sponsorships will be acknowledged in announcements before the event, on the ICS 2018 web site, during the conference, and in the proceedings.

    Platinum ($5,000+)

    • Each platinum sponsor will be named as the exclusive sponsor for one ICS main social event or other sponsorship opportunity, and identified as such through a public announcement and a poster.
    • All platinum sponsors may supply a limited amount of materials to be given to each attendee at registration (for example a pamphlet, a CD, or token gift)
    • All platinum sponsors will be listed (by logo) at the top of a list of sponsors that will be shown on the conference web site, the conference program, on the conference bag, and a poster at the conference registration area.
    • All platinum sponsors receive one complimentary full registration, which includes tutorials and workshops.
    • All platinum sponsors are given the opportunity to reserve a poster panel to be displayed at the poster session on Wednesday evening.
    • Platinum sponsors will also have the opportunity to display materials on an industrial table set up during the main technical paper sessions. 

    Gold ($3,000 – $4,999)

    • The gold sponsor will be named as the exclusive sponsor for an ICS lunch, and identified as such through public advertisement at the event.
    • All gold sponsors may supply a limited amount of materials to be given to each attendee at registration (for example a pamphlet, a CD, or token gift)
    • All gold sponsors will be listed (by logo) in the middle of a list of sponsors that will be shown on the conference web site, the conference program, the conference bag, and a poster at the conference registration area.
    • All gold sponsors receive one complimentary registration for the conference technical program.
    • All gold sponsors are given the opportunity to reserve a poster panel to be displayed at the poster session on Wednesday evening.

    Silver ($1,000 – $2,999)

    • Silver sponsors will be named as a sponsor of a day’s morning and afternoon breaks, or a tutorial/workshop breakfast, and identified as such through public advertisement at the event.
    • All silver sponsors will be listed (by logo) at the bottom of a list of sponsors that will be shown on the conference web site, the conference program, the conference bag, and a poster at the conference registration area.
    • All silver sponsors receive one complimentary registration for the conference technical program.
    • All silver sponsors are given the opportunity to reserve a poster panel to be displayed at the poster session on Wednesday evening.

    Bronze ($500 – $999)

    • All bronze sponsors will be listed (by logo) at the bottom of a list of sponsors that will be shown on the conference website, the conference program, the conference bag, and a poster at the conference registration area.

    For more information about ICS sponsorship, please see the ICS website or contact Lei Liu (liulei2010@ict.ac.cn), the General Chair for ICS 2018.

    Guidelines for Submissions to ICS 2018

    This document is intended to serve as a sample for submissions to the International Conference on Supercomputing (ICS)-2018. We provide some guidelines that authors should follow when submitting their papers to the conference.

    1 Introduction

    This document provides the formatting instructions for submissions to the International Conference on Supercomputing, 2018. In an effort to respect the efforts of reviewers and in the interest of fairness to all prospective authors, we request that all submissions to ICS-2018 follow the formatting and submission rules detailed below. Submissions that violate these instructions may not be reviewed, at the discretion of the program chair(s), in order to maintain a review process that is fair to all potential authors.

    An example submission (formatted using the ICS-2018 submission format) that complies with the submission and formatting guidelines can be downloaded from Sample PDF. This document is generated from the ACM template by using the “sigconf” style.

    Submission Site:

    The submission is over.
    Abstract/paper registration deadline:
    January 19, 2018 (AOE)

    Full paper submission deadline:
    January 26, 2018 (AOE)
    Jan 29, 2018. 11:59:59 pm EST (Hard Deadline)

    2 Paper Preparation Instructions

    2.1 Paper Formatting

    Papers must be submitted in PDF format and should contain a maximum of 10 pages of single-spaced two-column text, including references and appendixes. Please prepare your paper by using the “sigconf” style in the ACM template (For example, if you use LaTex, please download this sample: ICS-2018 Latex Template that was prepared with that template. Please NOTE: This sample package uses free packages and fonts available in all major TEX distributions like TEXLive, MikTEX, MacTEX 2015 and later. If you have older distributions your documents will have incorrect fonts.) If you use a different software package rather than LaTex or Word to typeset your paper, then please adhere to the guidelines mentioned in following table.

    Field Value
    File format PDF
    Page limit 10 pages (including references/appendixes)
    Paper size US Letter (8.5in x 11in)
    Top margin 1.04in
    Bottom margin 1.11in
    Left margin 0.75in
    Right margin 0.75in
    Body 2-column, single-spaced
    Body font 9pt
    Abstract font 9pt (regular font)
    Section heading font 11pt, bold, Capitalized
    Subsection heading font 11pt, bold
    Caption font 9pt, bold
    References 7pt, within page limit, list all author’s names

    Please ensure that you include page numbers with your submission. This makes it easier for the reviewers to refer to different parts of your paper when they provide comments.

    2.2 Content

    Author List. Reviewing will be double blind; therefore, please do not include any author names on any submitted documents except in the space provided on the submission form. You must also ensure that the metadata included in the PDF does not give away the authors. If you are improving upon your prior work, refer to your prior work in the third person and include a full citation for the work in the bibliography. For example, if you are building on your own prior work in the papers [1, 2, 3], you would say something like: "While the authors of [1, 2, 3] did X, Y, and Z, this paper additionally does W, and is therefore much better.” Do NOT omit or anonymize references for blind review. There is one exception to this for your own prior work that appeared in IEEE CAL, workshops without archived proceedings, etc. as discussed later in this document.

    Figures and Tables. Ensure that the figures and tables are legible. Please also ensure that you refer to your figures in the main text. Many reviewers print the papers in gray-scale. Therefore, if you use colors for your figures, ensure that the different colors are highly distinguishable in gray-scale.

    References. Please notice that the reference is within 10-page limitation. Each reference must explicitly list all authors of the paper. Papers not meeting this requirement will be rejected. Knowing all authors of related work will help find the best reviewers.

    3 Paper Submission Instructions

    3.1 Declaring Authors

    Declare all the authors of the paper upfront. Addition/removal of authors once the paper is accepted will have to be approved by the program chair, since it potentially undermines the goal of eliminating conflicts for reviewer assignment.

    3.2 Conflict Responsibilities

    The authors must select the PC members who have conflicts of interest with the submission. This includes past advisors and students, people with the same affiliation, and any recent (~2 years) coauthors and collaborators. Conflicts are needed to ensure appropriate assignment of reviewers. If a paper is found to have an undeclared conflict that causes a problem OR if a paper is found to declare false conflicts in order to abuse or “game” the review system, the paper may be rejected.

    3.3 Concurrent Submissions and Workshops

    By submitting a manuscript to ICS-2018, the authors guarantee that the manuscript has not been previously published or accepted for publication in a substantially similar form in any conference, journal, or workshop. The only exceptions are (1) workshops without archived proceedings such as in the ACM digital library (or where the authors chose not to have their paper appear in the archived proceedings), or (2) venues, such as IEEE CAL, where there is an explicit policy that such publication does not preclude longer conference submissions. These are not considered prior publications. Technical reports and papers posted on public social media sites, Web pages, or online repositories, such as arxiv.org, are not considered prior publications either. In such exceptional cases, the submitted manuscript may ignore the above work to preserve author anonymity. This information must, however, be provided on the submission form – the program chair(s) will make this information available to reviewers if it becomes necessary to ensure a fair review. (This policy will be explicitly conveyed to the reviewers as well.) The authors also guarantee that no paper that contains significant overlap with the contributions of the submitted paper will be under review for any other conference, journal, or workshop during the ICS-2018 review period. Violation of any of these conditions will lead to rejection. As always, if you are in doubt, it is best to contact the program chair(s).
    Finally, we also note that the ACM Plagiarism Policy (http://www.acm.org/publications/policies/plagiarism_policy) covers a range of ethical issues concerning the misrepresentation of other works or one’s own work.

    Example References

    [1] Leslie Lamport. LATEX: A Document Preparation System. Addison-Wesley, Reading, Massachusetts, 2nd Edition, 1994.
    [2] Firstname1 Lastname1 and Firstname2 Lastname2. A very nice paper to cite. In Proceedings of the 33rd Annual ACM SIGPLAN Conference on Programming Language Design and Implementation, 2012.
    [3] Firstname1 Lastname1, Firstname2 Lastname2, and Firstname3 Lastname3. Another very nice paper to cite. In Proceedings of the 22nd ACM Symposium on Operating Systems Principles, 2011.
    [4] Firstname1 Lastname1, Firstname2 Lastname2, Firstname3 Lastname3, Firstname4 Lastname4, and Firstname5 Lastname5. Yet another very nice paper to cite, with many author names all spelled out. In Proceedings of the 38th Annual International Symposium on Computer Architecture, 2011.